Gepostet am: 24.11.2015 20:17:44
I have finalized the coding of all modules of the new filter. But I still have no full bitmatch with my models written in C. And, as expected, the resource utilisation is catastrophically high. I will have to reduce the number of multipliers by resource sharing to fit it into the FPGA. Once the bitmatch is complete I can do simulation runs that should give a first impression of the new filters.