Next Steps

The next steps are:

  1. Finalize the implementation of the new filter approach  
  2. Solve a problem with the clocking
    • currently I still need the ~8MHz dot clock from VIC as a helper clock
  3. Make some breadboard experiments for the missing features
    • Paddle readout
    • Audio-In
  4. Make a PCB layout and find someone who can solder BGA devices
  5. Produce a small lot of prototype PCBs and distribute them to "selected" people for testing
  6. Release FPGA code to the public
  7. Continue debugging to make it perfect