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Some progress on the filters

posted Nov 24, 2015, 12:17 PM by andi6510 The FPGASID Project
I have finalized the coding of all modules of the new filter. But I still have no full bitmatch with my models written in C. And, as expected, the resource utilisation is catastrophically high. I will have to reduce the number of multipliers by resource sharing to fit it into the FPGA. Once the bitmatch is complete I can do simulation runs that should give a first impression of the new filters.
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