As promissed, here is a first audio file from the new filter implementation. It is based on simulation because I had a technical problem with my recording hardware.On the Project Details page I added this file along with some information about the Verilog simulation. It's not very detailed. But you can get an impression what it means to simulate Verilog code.
The audiofile comes with the simulated signal from FPGASID on the left channel and with the signal generated by the RESID library on the right channel. So no real 6581 can be heard in that file - everything is entirely based on number crunching (which took about 15 hours btw)
So here it is: CaerAisling (simulation FPGASID vs. RESID emulation)
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