After the new filter approach was implemented, I did some extensive testing of the filters. And of course I found that not everything was working perfectly well. Especially at low cutoff frequencies with high resonance values, the filters stopped working.
So I had to refine the design even further.
Doing this, I ran into a couple of limits caused by the relatively low clock of 8 MHz driving the filter part. It was simply impossible to find enough clock cycles for the complex filter calculations. At that time I had three clock domains in the design: A 1 MHz bus clock for the registers, 8 MHz for the SID and a third clock of 64 MHz that was used only for the delta-sigma DA-converter at the output.
I decided to move the complete design to the 64MHz domain and remove the intermediate clock of 8 MHz completely. In a way this simplified the design because clock domain crossings are always a bit tricky to handle. But on the other hand the higher clock rate puts more demands on timing closure. In the past days I was busy adding pipelining flip-flops and adjust the constraints in order to achieve full timing closure even for 64 MHz.
Today I finished that work. The result is really astonishing! I came really close to the sound of one of my 6581 SIDs (0184). A second SID, that I used for testing so far (2383), has a very funny band-pass filter sound - so I will not use it for comparison anymore because it is not a very typical one.
In the Project Details I have added another audiofile. You can listen to my latest achievement there.
Regarding the FPGA resources, I have saved two multipliers by further resource sharing. OK, I admit that's not very much. And well, I have also used up all available memory for lookup tables. I even had to use some space in the embedded flash memory of the FPGA for the mixed waveform wave-tables. This is a pitty because I wanted to have these user programmable which is not possible anymore.
There is some potential for memory saving. But this could affect the sound quality. So I will not put this on top priority.
Project updates >