After a successful presentation of FPGASID at the CC2015 in Thionville I regained the energy to continue the perfection of the filter circuits. The current implementation mostly lacks of the missing digital representation of the non-linearity inside the original SID chip. I was considering to implement a number of lookup tables to do this but the size of these tables would exceed the maximum FPGA size by far. I am now using linear approximation of such non-linear curves which reduces the size drastically but requires a number of multipliers which may be too much for my FPGA again. Once I have finalized this I am expecting much better results on the filters but I also expect the FPGA code to grow significantly.
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