Here are a couple of websites related to SID topics
The FPGASID project is not the first project implementing the SID in a FPGA. Here are a couple of other projects that are dealing with the same topic.
I have looked at all of them and studied their VHDL or Verilog code (as far as it is available). But then finally I decided to write the FPGASID code completely from scratch. This is giving me more freedom in architectural and technical decisions. And it avoids any copyright infringement.
SID player on Papilio FPGA board
Another reinvention of the wheel
Earlier attempt to do a SID with filters
The Chameleon Module also incorporates a SID implementation (closed source)
The goal of a drop-in replacement has also been achieved by the very nice and advanced SWINSID project. Rather than FPGA, this project is using a software approach for the emulation.
SID Emulation in Software
The by far most advanced and most accurate SID emulation is done by the RESID library which is part of JSIDPLAY2 (in java)
…and it’s C++ fork in VICE:
The FPGASID development is using the RESID library as a reference and tries to match it as exactly as possible. Unfortunately, a complete bitmatch is not possible. The huge and complex RESID model does not fit into an affordable FPGA. The goal is, to optimize the FPGASID implementation size to a minimum while makeing the behaviour as similar as possible, even on a small footprint FPGAs.
A warm thanks goes to all the project members working on RESID. Especially to Dag Lem for kicking this off some years ago and to Antti Lankila for his SID distortion model and the very detailed investigation of the SID chip on die level.